----------------------------------------------------------------------------------
-- Company: 
-- tianszzz 
-- 
-- Create Date:    18:34:38 10/23/2021 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity ls161 is
    port(
		load_n : in STD_LOGIC;
		clr_n  : in STD_LOGIC;
		clk    : in STD_LOGIC;		  
		ent  : in STD_LOGIC;
		enp  : in STD_LOGIC;
		A      : in STD_LOGIC;
		B      : in STD_LOGIC;
		C      : in STD_LOGIC;
		D      : in STD_LOGIC;		  
		QA     : out STD_LOGIC;
		QB     : out STD_LOGIC;
		QC     : out STD_LOGIC;
		QD     : out STD_LOGIC;	
        rco    : out STD_LOGIC	   
	 );
	 
end ls161;

ARCHITECTURE Behavioral OF ls161 IS
   
   SIGNAL temp_in :  std_logic_vector(3 DOWNTO 0) := "0000";
   SIGNAL temp_out :  std_logic_vector(3 DOWNTO 0) := "0000";	
BEGIN
   QA <= temp_out(0);
   QB <= temp_out(1);
   QC <= temp_out(2);
   QD <= temp_out(3);
   temp_in <= D & C & B & A;
	
   PROCESS (clk,clr_n)
   BEGIN
        if(clr_n = '0') then
		    temp_out <= "0000";
        elsif (clk'EVENT AND clk = '1') THEN
            if (load_n = '0') THEN
                temp_out <= temp_in;
            elsif (ent = '1' AND enp = '1') THEN
           --     if (temp_out = "1001") THEN
				--    temp_out <= "0000";
             --   else
                    temp_out <= temp_out + "0001";	
              --  end if;
            else
                temp_out <= temp_out;			
            END IF;
        END IF;
   END PROCESS;

   process(temp_out)   
	begin
	    if(temp_out = "1111") then
		     rco <= '1'; 
	    else
		     rco <= '0'; 
       END IF;			  
   END PROCESS;  
   
END Behavioral;

